ASIC Physical Design Trainee
RV VLSI and Embedded Systems Design Center (RV SKILLS) (July 2023 - Feb 2024)
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As a full time on campus trainee at RV-VLSI I'm working on block level physical design flow of a multicore subsystem in deep submicron technology nodes.
- Experience with 40nm technology including understanding of RM of synopsis for TSMC deep submicron technology - 20nm, 16/14nm, 10nm and 7nm.
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RTL to GDSII for a block of 34 macros including communication, image processing and cryptography IP's
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Automating various tasks in the flow using TCL, perl and python.
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Knowledge of VCS , PrimeTime and ICC2.
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IR Drop analysis
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Timing driven placement and low power design
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Clock Tree Synthesis
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Static timing analysis
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Design for Testability ( 2 scan Chains)
Recommendation Letter
Research Intern
Defence Research and Development Organization (DRDO) (Aug 2021 - Dec 2021)
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Research Intern at the Defence Research and Development Organization - Defence Bioelectronics and Electromedical Laboratory (DEBEL).
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Performed thorough research work on ECG and EEG signals and developing a heart rate detection method with filtering for an ECG Signal. Also performed research work on compressive sensing implementation of acquiring ECG signals (Github)